Job Description

Fab Sort Manufacturing (FSM) is responsible for the production of all Intel silicon using some of the world's most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and 2 new greenfield sites in Ohio and Germany.

As part of Intel's IDM2.0 strategy, FSM is rapidly expanding its operation to deliver output for both internal and foundry customers with state-of-the-art technologies arriving in High-Volume Manufacturing (HVM) at a 2-year cadence going forward. Intel recently created HVM Global Yield organization in FSM to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development team and FSM fab managers.

This job requisition is to seek FEOL (Front-End-Of-Line) Process Integration Development engineering roles in FSM HVM Global Yield organization, reporting to FEOL Process Integration Engineering Development manager. Selected candidates will work with other members in FEOL integration, other teams in Global Yield org, fab module, yield, and TD team members to achieve yield ramp-up and process optimization in early production stage, supporting internal and external customers.

FEOL (Front-End-Of-Line) Integration Development engineers' responsibilities include (but not limited to):

• Own engineering projects to execute HVM yield roadmap, device targeting and attain performance targets.

• Collaborate with Technology Development and Local Yield teams to import new technology to production fabs.

• Work with FEOL/BEOL Integration, Device, Defect Reduction and Yield Analysis team members to identify root cause of yield/performance issues and implement mitigation plan in defined timeline to meet committed production yield/performance targets and to support fast paced yield ramp-up in high-volume manufacturing phases.

• Perform feasibility studies, plan and conduct experiments to fully characterize the process throughout the development cycle and to improve performance for each specific product.

• Own NPI (New Product Introduction) in production fabs and perform product-specific process optimizations to meet foundry customers specifications and requirements.

• Own engineering projects in partnership with Local Yield teams to improve product yield, quality, device performance and to reduce wafer cost.

• Engineering support for technical interactions with internal and external customers.

Candidate should possess the following behavioral skills:

• Must demonstrate solid communication skills.

• Ability to work with multi-functional, multi-cultural teams.

• Demonstrated interpersonal skills including influencing, engaging, and motivating.

• Problem-solving technique with strong self-initiative and self-learning capabilities.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's degree in science and engineering major, with at least 12 years of experience in advanced node semiconductor industry in FEOL Process Integration (preferably in one (or more) of the following segments: Fin, Gate or PC, Spacer/Source-Drain or Junctions, RMG (Replacement Metal Gate), Contact / MOL (Middle of the Line)). Level of experience will be considered in determining applicants job grade.

• Working level understanding on Device Physics and experience in advanced nodes (FinFET technology, GAA (Gate-All-Around)) in development or high-volume manufacturing.

• Basic understanding and collaboration experience with processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.

Preferred Qualifications:

• Advanced degree (Master's or Ph.D.) in Electrical Engineering, Physics, Chemistry or Materials Science major is preferred, with at least 8 years of experience.

• Experience in project/program management and/or Task Force Team lead.

• Ability to leverage big data analysis to identify process design weaknesses and/or manufacturing weaknesses in order to propose corrective, data-based solutions.

• Ability to extracts insights from structured and unstructured data by quickly synthesizing large volumes of data, and applying statistics and machine learning.

• Experience in new semiconductor technology development.

• Experience in serving external Foundry customers through technical interactions.

• Experience in GAA (Gate-All-Around) technology architecture.

• Experience in Statistics and Machine Learning.

#foundry

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.